Cycle-based logic simulation is applicable to synchronous digital systems and may be utilized to verify the functional correctness of a digital design. Cycle-based simulators use algorithms that eliminate unnecessary calculations to achieve improved performance in verifying system functionality. Typically, in a cycle-based logic simulator the entire system is evaluated once at the end of each clock cycle. Discrete component evaluations and re-evaluations are typically unnecessary upon the occurrence of every event.
HDL simulations may be event driven or cycle-based. Event driven simulations propagate a change in state from one set of circuit elements to another. Event driven simulators may record relative timing information of the change in state so that timing and functional correctness may be verified. Cycle-based HDL simulations also simulate a change in state from one set of circuit elements to another. Cycle-based HDL simulations, however, evaluate the state of the system once at the end of each clock cycle. While specific intra-cycle timing information is not available, simulation speed is improved.
HDL simulations may be executed on reconfigurable hardware, such as a field programmable gate array (FPGA) chip. The FPGA allows dedicated hardware to be configured to match the HDL code. FPGA hardware provides a method to improve the simulation time. As the design changes, the time required to reconfigure the FPGA arrangement may prohibit many iterations. Also, the number of FPGA chips required for complex designs may be relatively large.
HDL simulations may also be executed on general purpose processors. General purpose processors, including parallel general purpose processors, are not designed specifically for HDL simulations. HDL simulations require a large number of operations of inputs and outputs that use bit-wise operations.
Large logic simulations are frequently executed on parallel or massively parallel computing systems. For example, parallel computing systems may be specifically designed massively parallel processing (MPP) systems or equally a collection, or “farm,” of connected general purpose processing systems. FIG. 1 shows a block diagram of a typical parallel computing system (100) used to simulate a HDL logic design. Multiple processor arrays (112a, 112b, 112n) are available to simulate the HDL logic design. A host computer (116), with associated data store (117), controls a simulation of the logic design that executes on one or more of the processor arrays (112a, 112b, 112n) through an interconnect switch (118). The processor arrays (112a, 112b, 112n) may be a collection of processing elements or multiple general purpose processors. The interconnect switch (118) may be a specifically designed interconnect or a general purpose communication system, for example, an Ethernet network.
A general purpose computer (120) with a human interface (122), such as a GUI or a command line interface, together with the host computer (116) support common functions of a simulation environment. These functions may include, but are not limited to, an interactive display, modification of the simulation state, setting of execution breakpoints based on simulation times and states, use of test vectors files and trace files, use of HDL modules that execute on the host computer and are called from the processor arrays, check pointing and restoration of running simulations, the generation of value change dump files compatible with waveform analysis tools, and single execution of a clock cycle.
While simulating a hardware design in an MPP environment, at least two goals exist. First, the multiple processors should be effectively controlled. Second, the multiple processors should run effectively. One way to control an MPP system, for instance, is to use the host computer, or another similar mechanism, to exert control on the MPP system by essentially telling the processors what to do and when to run. This can be accomplished, for instance, by sending packets of information to the processors, which they act upon.
In contrast to controlling a MPP system, running a MPP system involves connecting the processors in such a way that they can communicate with one another and pass data and instructions between each other so that at all times, the majority of the processors can be active simultaneously. For instance, a processor may often wait for the result of a computation performed by another processor in order to use the result to perform its own computation. To accomplish this task while running, a correct path for the data is required.
Typically processors interconnect and pass data between one another using pins. Pins are designed to carry an electrical charge and are able to connect to the pins of other processors. The number of pins that each processor has, however, is limited and to both control and run an MPP system involves two distinct types of communication. Thus, in typical MPP systems, the amount of pins required to perform both tasks quickly exceeds the number of pins available on the processor. Therefore, conservation of the amount of pins required to control and run an MPP system is desirable.